module tb_axi_sram();

  reg clk;
  reg rst_n;
  
  // AXI Signals
  reg [15:0] awaddr;
  reg awvalid;
  wire awready;
  
  reg [7:0] wdata;
  reg wvalid;
  wire wready;
  
  wire [1:0] bresp;
  wire bvalid;
  reg bready;
  
  // SRAM Interface
  reg sram_cs;
  wire sram_we;
  wire [9:0] sram_addr;
  reg [7:0] sram_din;
  wire [7:0] sram_dout;



  // Instantiate Modules
    sram_crossbar #(
    .DATA_WIDTH(8),
    .SRAM_ADDR_WIDTH(10),
    .NUM_SRAM(64)
    ) crossbar_inst (
    .clk(clk),
    .rst_n(rst_n),
    .cs(sram_cs),
    .wen(sram_we),
    .addr(awaddr),
    .wdata(wdata),
    .rdata(sram_dout),
    .awvalid(awvalid),
    .awready(awready),
    .wvalid(wvalid),
    .wready(wready),
    .bresp(bresp),
    .bvalid(bvalid)
    );


    initial begin
    clk = 0;
    forever #5 clk = ~clk;
    end
  // Clock generation
    initial begin
    // 初始化
    rst_n = 0;
    awaddr = 16'h0;
    awvalid = 0;
    wdata = 8'h0;    // 注意AXI协议中数据应通过wdata传递
    wvalid = 0;
    bready = 0;

    // 复位释放
    #20 rst_n = 1;
    #10;

    // 启动写交易（分步握手）
    // 1. 发送地址
    awaddr = 16'h73F;    // Bank0地址0x3F（bank_sel=0）
    awvalid = 1;
    while (!awready) @(posedge clk);  // 等待地址握手
    @(negedge clk);
    awvalid = 0;

    // 2. 发送数据
    wdata = 8'hA5;
    wvalid = 1;
    sram_cs = 1;
    while (!wready) @(posedge clk);   // 等待数据握手
    @(negedge clk);
    wvalid = 0;

    // 3. 等待响应
    while (!bvalid) @(posedge clk);
    bready = 1;
    @(negedge clk);
    bready = 0;
    // begin #1000; $error("响应超时"); end
    // join_any
    // disable fork;
    // #20;

    // Verify write
    // if (crossbar_inst.SRAM_BANK[bank_sel].sram_inst.mem[sram_addr] == wdata) begin
    //     $display("TEST PASSED: Data %h written to Bank%d Address %h", 
    //             wdata, bank_sel, sram_addr);
    // end else begin
    //     $display("TEST FAILED: Bank%d Addr %h Expected %h, Got %h",
    //             bank_sel, sram_addr, wdata,
    //             crossbar_inst.SRAM_BANK[bank_sel].sram_inst.mem[sram_addr]);
    // end
    $finish;
  end

endmodule